There are many types of bus standards that are employed to implement connectivity of components in a computer. For example, PCIe (Peripheral Component Interconnect express) is a high-speed serial computer expansion bus standard that allows numerous types of peripheral devices to interconnect with other devices within a computer system.
Most widely adopted standards are maintained by organizations composed of interested technology experts and industry members. For PCIe, this standard is maintained by the PCIe-SIG (PCIe Special Interest Group) based upon a formal specification that details specific requirements for components to be in compliance with the standard. Designers and manufacturers will often seek formal certification of compliance to verify the compatibility of offered products to the PCIe standard. By obtaining this type of certification, this signals to the potential customers that the offered products will in normal usage be compatible with the standard and to devices/products offered by other manufacturers which are also certified to the same standard.
Electronic design IP (Intellectual Property) are portions or blocks of electronic designs to implement specific functionality, which are used or licensed by designers to insert into a larger electronic design. Such electronic design IP are often created by domain experts in a given technical space, and allow the licensees of such IP to avoid having to implement specialized designs that may be outside their technical focus. This approach also allows the licensees to be able to concentrate their limited engineering resources upon their overall product design rather than to “re-create the wheel” by re-implementing functional blocks that have already been usefully developed and de-bugged by others.
When such electronic design IP is intended to be employed in compliance with a standard such as PCIe, that IP may need to be taken to a compliance workshop to ensure that it complies with the requirements of the standard's formal specifications. This type of compliance processing for design IP can be taken by fabricating the design onto a testchip (“TC”) in a daughter card, and then performing a validation phase between that daughter card/testchip and a PCIe controller.
The specific problems addressed by this document are the inefficiencies caused by conventional compliance setups for standards such as PCIe for electronic design IP. A conventional PCIe compliance setup may contain a PCIe PHY (PCIe physical layer) testchip in a daughter card and the PCIe Controller/other required logics in another hardware component (e.g., implemented using a programmable device such as a FPGA device (field programmable gate array device), referred to herein without limitation as “FPGA”). Due to large board delays between the daughter card and the programmable device, as well as variable skew between PIPE (PHY Interface for PCI Express) data/control bus due to TC bump map, board routing, FPGA pin mapping, and similar issues, single cycle timing closure is not possible between the TC and FPGA.
This issue is due to the fact that data sent/received at the FPGA with a FPGA clock may not be source synchronous with data received/sent at the testchip with the testchip clock, and hence there may be variances in the delays for the multiple clocks. To address this issue, one possible approach is to take the clock between the testchip and the FPGA, feed that clock as an input into a respective MMCM (Multi-Mode Clock Manager) at the receiving device, and then generate an output clock. An engineer can manually adjust the MMCM offset, check the results (e.g., using an oscilloscope), and then continue to adjust the offset until the clocks are accurately aligned between the FPGA and the testchip.
A significant problem with this approach is the severe inefficiency of requiring a manpower-intensive process that must be performed where there are potentially multiple rounds of manual adjustments required per chip to achieve an acceptable result. In addition, whatever offset that was found acceptable for one testchip may not necessarily be acceptable for any other testchip, due to differences between each testchip's PVT (process, voltage, temperature) corners and variations. As such, the same tedious process may need to be repeated in its entirety for each and every testchip.
Therefore, for at least these reasons, there is a need for an improved approach to implement clock alignments between a testchip and its corresponding controller device.